The present invention relates to a TDMOS (Trench Double diffused MOS power device and a method of fabricating a vertical TDMOS power device. More particularly, the present invention relates to a method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique to require only 3 masks and the TDMOS power device of the same.
In general, TDMOS is a power device operable with middle voltage and middle current and used in stepping motor, driving IC of FED (Field Emission Display) and the like. Compared with a general DMOS, the TDMOS is fabricated in complex processes using at least four masks. Because cost for masks occupies very large portion of cost for fabricating a semiconductor device, a method of fabricating a semiconductor device is required, which is capable of decreasing the number of masks used in fabrication thereof.
Also, the conventional method of fabricating the TDMOS, it is known, has many problems in leakage current, breakdown voltage and reliability, and thus a method of fabricating a TDMOS device in a more simple and reliable way is required.
Therefore, the present invention is made in order to solve the problems described above.
An object of the present invention is to provide a method of fabricating a vertical TDMOS power device using a trench sidewall and a self-align technique to require only 3 masks, which is improved in leakage current, breakdown voltage and reliability.
The above objects can be accomplished by a method of fabricating a vertical TDMOS power device, the method comprising steps of: forming a first insulating film pattern on a predetermined region of a substrate of a first conductivity; forming a channel layer by implanting a ion of a second conductivity on said substrate using said first insulating film pattern as a mask and then diffusing said ion of said second conductivity; forming a trench by forming a sidewall spacer on a sidewall of said insulating film pattern and etching said channel layer to expose said substrate of said first conductivity; forming an impurity region in a region of said channel layer adjacent to said trench and in a region of said substrate of said first conductivity under said trench by removing said sidewall spacer and then implanting an ion of said first conductivity using said first insulating film pattern as a mask; forming a gate oxide film on a surface of said trench; forming a gate electrode within said trench; forming a body contact by forming a second insulating film pattern on said gate electrode, removing said first insulating film pattern and then implanting a ion of said second conductivity using said second insulating film as a mask; and forming a metal film for an electrode on said impurity region of said channel layer adjacent to said trench and on said body contact.
It is preferable that an insulating film having an etching selectivity over said first insulating film pattern is formed on a surface of said substrate of said first conductivity.
Also, it is preferable that said sidewall spacer is formed by forming LTO film on the resultant surface and then carrying out an etch-back.
It is more preferable that said LTO film has an etching selectivity over said first insulating film pattern.
It is preferable that in said step of forming said gate oxide film, said gate oxide film on a bottom of said trench is formed thicker than said oxide film on a sidewall of said trench.
Also, it is preferable that the method of fabricating a vertical TDMOS power device further comprises, before said step of forming said gate oxide film, a step of growing an sacrificial oxide film and then removing said sacrificial oxide film, in order to improving a surface state of said trench.
It is preferable that said second insulating film pattern has an etching selectivity over said first insulating film pattern.
Also, the above objects can be accomplished by a vertical TDMOS power device, comprising: a substrate of a first conductivity; a channel layer of a second conductivity formed on said substrate; a trench in a predetermined region of said channel layer; a gate oxide film formed on a surface of said trench; a gate electrode formed on said gate oxide film in said trench; an impurity region of said first conductivity formed on a region of said channel layer adjacent to said trench and on said substrate of said first conductivity under said trench; a body contact of said second conductivity formed on said channel layer, adjacent to said impurity region of said first conductivity; and a metal film connected to said impurity region and said body contact.
It is preferable that, in said gate oxide film on the surface of said trench, said gate oxide film formed on a bottom of said trench is thicker than said oxide film formed on a sidewall of said trench.